The present invention relates to a semiconductor memory device called DRAM (dynamic random access memory), or the like, and specifically to a structure of a semiconductor memory device which is associated with a power supply circuit.
In a semiconductor memory device, such as a DRAM, or the like, a predetermined voltage is applied to a word line, and a potential difference generated on a bit line by application of the predetermined voltage is amplified by a sense amplifier, whereby stored information is read out. The supply voltage supplied to a word driver which drives the word line is set to a level higher than a supply voltage supplied to the sense amplifier, or the like, such that the potential difference on the bit line becomes as large as possible.
In recent years, meanwhile, the margins for a variation in the supply voltage supplied from a device external to the semiconductor memory device have been decreasing as the semiconductor process becomes finer or as the operation voltage becomes lower. In order to overcome such a problem, a regulated power supply circuit is provided inside the semiconductor memory device such that an internal supply voltage generated by decreasing and stabilizing an external supply voltage is supplied to a sense amplifier, or the like. The once decreased and stabilized internal supply voltage is increased by a pump-up circuit and supplied to the word driver (see, for example, Japanese Unexamined Patent Publication No. 6-140889).
However, in the above conventional semiconductor memory device, the degree of voltage conversion by the pump-up circuit is large because the once decreased internal supply voltage is increased before being supplied to the word driver. Therefore, the conversion efficiency of the voltage is low, and the circuit scale of the power supply circuit including the pump-up circuit and the area occupied by the power supply circuit are relatively large. These problems become more noticeable as the semiconductor process becomes finer for the purpose of increasing the storing density of the principal part of a memory circuit.